1. Explain how instruction set, compiler technology, CPU implementation and control, cache and memory hierarchy affect the CPU performance and justify its effects in terms of program length, clock rate and effective cycles per instruction (CPI).

2. Why do most RISC integer units use 32 general purpose registers Explain the relationship between the integer unit and the floating-point unit in most RISC processors using either scalar or superscalar organization.

3. Explain and compare the following four cache memory organizations in terms of hardware complexity, implementation cost and flexibility in implementing "block replacement algorithm"
Direct mapping cache
Fully associative cache
Set associative cache
Sector mapping cache

4. A pipeline is found to provide a speed up of 6·16 when operating at 100 MHz and an efficiency of 88%.
How many stages does have? What are MIPS and CPI performance levels


5. Define the following terms related to parallelism and dependence relation:

(a) Computational granularity Antidependence Bernstein conditions Degree of parallelism Communication latency

6. Compare the advantages and shortcomings in implementing private virtual memories and a globally shared virtual memory in a multicomputer system based on their latency, coherence, page migration and protection issues.

7. Consider the following pipeline reservation table:

<img src='./qimages/15615-7.jpg'>

(a) What are the forbidden latencies?
Draw the state transition diagram.
List all the simple and greedy cycles.
Determine the optimal constant latency cycle and the minimal average latency.
Determine the throughput of this pipeline with pipeline clock period t =20 ns.

8.(a) A magnitude-comparator circuit compares two unsigned numbers X and Y and produces three outputs Z1,Z2 and Z3, which indicate X X and X Y respectively. Show how to implement a magnitude comparator for 2-bit numbers using a single 16-input, 3-bit multiplexer of appropriate size.

9. Discuss the impact of the following design decisions on cache performance: Selection of a cache block (line) size pI, which is quite small. Selection of a cache block size, which is too big. Selection of an associativity level that is too small.

10. Consider the pipelined processor with a total evaluation time of six clock cycles. All successor stages must be used after each clock cycle.

<img src='./qimages/15615-10.jpg'>

(a) Specify the reservation table for this pipeline.
List the set of forbidden latencies between task initiations.
List all-greedy cycles from the state diagram. What is the maximum throughput of this pipeline?