1. Characterise the architectural operations of SIMD and MIMD computers.. Distinguish between multiprocessor and multicomputer on the basis of their structures, resource sharing and interprocessor communications.

2. Compare the instruction-set architecture in RISC and CISC processors.in terms of instruction formats, addressing modes and cycles per instructions (CPl). Also mention the difference between superscalar and VLIW architectures in terms of hardware and software requirements.

3. Explain the following terms associated with memory management: The role of a memory manager in an operating system kernel Demand paging memory system and Swapping memory system, with examples

4. Consider a cache and memory hierarchy with the following characteristics
M1: 16 K words, 50 ns access time
M2 :1Mwords, 400 ns access time

Assume eight-word cache blocks and a set-size of 256 words with set-associative mapping.
Show the mapping between M2 and Calculate the effective memory-access time with a cache hit ratio of h =0·95.

5. The hardware cost of a new m-stage, single function pipeline is approximated by 22 m 30. The latency of the function to be executed is 90 ns, if pipelining is not used. The pipelined implementation's interstage buffers are expected to add an additional 10 m ns to this latency. Estimate the number of stages needed to optimize the pipeline's performance/cost ratio.

6. Define the following terms related to modem processor technology:

(a) Processor design space Resource conflicts Hardwired versus Micro-coded control Unified versus Split caches Instruction issue rate

7. Consider an adder pipeline with four stages as -shown below. The pipeline consists of input lines X and output line Z and a register R.

<img src='./qimages/13290-7.jpg'> Assume that the elements of the vector A are fed into the pipeline through input one element per cycle. What is the minimum number of clock cycles required to compute the sum of an N-element vector
N L
1=1

Neglect the set-up time for the pipeline and consider as input into the pipeline by default in the absence of an operand.
Find the minimum vector length required to achieve half of the maximum speed-up.

8. Design a 16-bit priority encoder using two copies of an 8-bit priority encoder. Use additional gates of any standard type while designing, if required.

9. Instructions such as instruction that modify memory make it difficult to support precise interrupts in pipelined CPUs. Why is this so Outline a design method to solve this problem.

10. Consider the five-stage pipelined processor specified by the following reservation table:

<img src='./qimages/13290-10.jpg'>

(a) List the set of forbidden latencies and the collision vector.
Draw a state transition diagram showing all possible initial sequences without causing a collision in the pipeline.
Identify the greedy cycles among the simple cycle.
What will be the maximum throughput of this pipeline?