Exam Details
| Subject | computer organisation and architecture (cs, it) | |
| Paper | ||
| Exam / Course | b.tech(cs) | |
| Department | ||
| Organization | Dr. A.P.J. Abdul Kalam Government College | |
| Position | ||
| Exam Date | July, 2017 | |
| City, State | dadra nagar haveli, silvassa |
Question Paper
B B4B0072
Page 1 of 2
Total Pages: 2
Reg
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
FOURTH SEMESTER B.TECH DEGREE EXAMINATION, JULY 2017
Course Code: CS202
Course Name: COMPUTER ORGANISATION AND ARCHITECTURE IT)
Max. Marks: 100 Duration: 3 Hours
PART A
Answer all questions. Each carries 3 marks.
1 Differentiate between big-endian and little-endian byte assignments.
2 Design a 2x2 array multiplier.
3 Describe auto increment addressing mode with the help of an example.
4 Give the control sequence for execution of instruction Add[R2],R1 using a
single bus organization.
PART B
Answer any two questions. Each carries 9 marks.
5 Describe, with proper examples, the role of processor stack in subroutine call
and return.
Draw the flowchart for decimal multiplication.
6 Explain restoring method of division with the help of a flow chart.
Write notes on three address, two address and one address instructions, giving
example for each.
7 Explain single bus organization with the help of a diagram. Specify with
examples, how memory operations are done in the given organization.
Describe any 4 addressing modes with examples.
PART C
Answer all questions. Each carries 3 marks.
8 What are vectored interrupts?
9 Write notes on flash memory.
10 Briefly explain the LRU cache replacement algorithm
11 Describe centralized bus arbitration.
PART D
Answer any two questions. Each carries 9 marks.
12 Explain the architecture of USB with a diagram. What do you mean by split
bus operation in USB?
Write notes on static memories.
B B4B0072
Page 2 of 2
13 Differentiate between associative and set associative cache mapping with
examples.
Write notes on interrupt nesting. Explain how simultaneous interrupt requests
can be handled.
14 Discuss about the different types of Read only memories.
Explain with the help of timing diagrams, the input and output data transfers in
an asynchronous bus.
PART E
Answer any four questions. Each carries 10 marks.
15 Design a bus system for interconnecting four n bit registers
Design a 4bit combinational logic shifter
16 Briefly explain, with diagrams, the different methods for control organization
Write notes on microprogrammed CPU organisation.
17 Design an adder/subtractor circuit with one selection variable s and two inputs
A and B. When the circuit performs A+B and when s=1 it performs
by taking complement of B.
Write notes on status register.
18 Describe the different ways in which a general-purpose processor unit can be
organized.
Write notes on conditional control statements.
19 Explain with the help of a diagram, the working of microprogram sequencer.
20 Describe the steps in control logic design with the help of an example.
(Example can be realised using either hardwired or microprogrammed control
organization.)
Page 1 of 2
Total Pages: 2
Reg
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
FOURTH SEMESTER B.TECH DEGREE EXAMINATION, JULY 2017
Course Code: CS202
Course Name: COMPUTER ORGANISATION AND ARCHITECTURE IT)
Max. Marks: 100 Duration: 3 Hours
PART A
Answer all questions. Each carries 3 marks.
1 Differentiate between big-endian and little-endian byte assignments.
2 Design a 2x2 array multiplier.
3 Describe auto increment addressing mode with the help of an example.
4 Give the control sequence for execution of instruction Add[R2],R1 using a
single bus organization.
PART B
Answer any two questions. Each carries 9 marks.
5 Describe, with proper examples, the role of processor stack in subroutine call
and return.
Draw the flowchart for decimal multiplication.
6 Explain restoring method of division with the help of a flow chart.
Write notes on three address, two address and one address instructions, giving
example for each.
7 Explain single bus organization with the help of a diagram. Specify with
examples, how memory operations are done in the given organization.
Describe any 4 addressing modes with examples.
PART C
Answer all questions. Each carries 3 marks.
8 What are vectored interrupts?
9 Write notes on flash memory.
10 Briefly explain the LRU cache replacement algorithm
11 Describe centralized bus arbitration.
PART D
Answer any two questions. Each carries 9 marks.
12 Explain the architecture of USB with a diagram. What do you mean by split
bus operation in USB?
Write notes on static memories.
B B4B0072
Page 2 of 2
13 Differentiate between associative and set associative cache mapping with
examples.
Write notes on interrupt nesting. Explain how simultaneous interrupt requests
can be handled.
14 Discuss about the different types of Read only memories.
Explain with the help of timing diagrams, the input and output data transfers in
an asynchronous bus.
PART E
Answer any four questions. Each carries 10 marks.
15 Design a bus system for interconnecting four n bit registers
Design a 4bit combinational logic shifter
16 Briefly explain, with diagrams, the different methods for control organization
Write notes on microprogrammed CPU organisation.
17 Design an adder/subtractor circuit with one selection variable s and two inputs
A and B. When the circuit performs A+B and when s=1 it performs
by taking complement of B.
Write notes on status register.
18 Describe the different ways in which a general-purpose processor unit can be
organized.
Write notes on conditional control statements.
19 Explain with the help of a diagram, the working of microprogram sequencer.
20 Describe the steps in control logic design with the help of an example.
(Example can be realised using either hardwired or microprogrammed control
organization.)
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