B B4810 Pages: 2
Page 1 of 2
Reg
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
FOURTH SEMESTER B.TECH DEGREE EXAMINATION, APRIL 2018
Course Code: CS202
Course Name: COMPUTER ORGANIZATION AND ARCHITECTURE IT)
Max. Marks: 100 Duration: 3 Hours
PART A
Answer all questions, each carries 3 marks Marks
1 With a neat diagram, explain the internal architecture of the CPU.
2 What are condition codes? List the different condition codes.
3 Prove that the worst case delay through an n × n array multiplier is 6(n − −1
gate delays.

4 Enumerate the sequence of actions involved in executing an unconditional
branch instruction.

PART B
Answer any two questions, each carries 9 marks
5 With the help of examples, explain the different addressing modes.
Register R6 is used in a program to point to the top of a stack containing 32-bit
numbers. Write a sequence of instructions using the Index, Autoincrement, and
Autodecrement addressing modes to perform each of the following tasks:
Pop the top two items off the stack, add them, then push the result onto the
stack.
Copy the fifth item from the top into register R3.
For each case, assume that the stack contains ten or more elements.

6 With the help of a diagram, describe the datapath inside the processor.
Discuss the different ways in which the return address can be saved during a
subroutine call. Which of these methods support subroutine nesting? Justify
your answer.

7 Write down the sequence of actions needed to fetch and execute the instruction:
Store R6, X(R8).

Multiply each of the following pairs of signed 2's-complement numbers using
the Booth algorithm. In each case, assume that A is the multiplicand and B is
the multiplier.
A 001011 and B 011011
ii) A 000111 and B 000111

PART C
Answer all questions, each carries 3 marks
8 Explain the functions of interface circuits.
9 List and describe the registers in a DMA interface.
B B4810 Pages: 2
Page 2 of 2
10 The cache block size in many computers is in the range of 32 to 128 bytes.
What would be the main advantages and disadvantages of making the size of
cache blocks larger?

11 What is flash memory?

PART D
Answer any two questions, each carries 9 marks
12 With a diagram, explain the PCI bus.
Write a note on the packet type formats of USB.
13 What are interrupts? List the sequence of steps following an interrupt request.
Describe semiconductor RAM memories.
14 With the help of an example, explain the different cache mapping function
A computer system has a main memory consisting of 1M 16-bit words. It also
has a 4K-word cache organized in the block-set-associative manner, with 4
blocks per set and 64 words per block. Calculate the number of bits in each of
the Tag, Set, and Word fields.

PART E
Answer any four questions, each carries 10 marks
15 Discuss shift and conditional control micro operations.
An 8-bit register A has one input x. The register operation is represented
symbolically as A7 ← Ai ← Ai+1 i ... 6. What is the function of
the register?

16 Compare vertical and horizontal microinstruction formats, giving examples.
17 With a diagram, explain how control signals are generated using hardwired
control.

18 Describe the purpose of microprogram sequencing. How is it carried out?
19 Draw the block diagram for the hardware that implements the following
statement x yz: AR ← AR BR where AR and BR are two n-bit
registers and and z are control variables. Include the logic gates for the
control function. (The symbol designates an OR operation in a control or
Boolean function and an arithmetic plus in a micro operation.)

20 Explain the design of status register.