Exam Details
Subject | digital logic design | |
Paper | ||
Exam / Course | b.tech | |
Department | ||
Organization | Institute Of Aeronautical Engineering | |
Position | ||
Exam Date | July, 2018 | |
City, State | telangana, hyderabad |
Question Paper
Hall Ticket No Question Paper Code: AEC020
INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
Four Year B.Tech III Semester End Examinations (Supplementary) July, 2018
Regulation: IARE R16
DIGITAL LOGIC DESIGN
Time: 3 Hours (Common to CSE IT) Max Marks: 70
Answer ONE Question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
UNIT I
1. Perform the subtraction operation using complement of the subtrahend
i. (5C)16 (3F)16
ii. (C0)16 (7A)16
Convert the following to the designated bases
a. (1000)2 to gray
b. (22:64)10 to )16
c. (A72F)16 to
2. Write about binary logic in detail and explain binary addition and binary subtraction with
examples.
Explain why Excess- 3 is self complementing code with an example.
UNIT II
3. Write the truth table for DeMorgans theorem by taking an example.
Simplify the boolean function
11; 15) that has the don't-care conditions
4. Implement the following Boolean functions using the following logic
i. using NAND- NAND Realization
ii. using NOR- NOR Realization
Simplify the following using four- variable K-map
i. w0z xz x0y wx0z
ii. B0D A0BC0 AB0C ABC0
Page 1 of 2
UNIT III
5. Explain the working of 2-bit magnitude comparator with the help truth table and logic diagram.
Enumerate the implementation of full-adder using two half-adders and an OR gate, for the
following boolean expressions:
S x0y0z x0yz0 xy0z0 xyz
C xy xz yz
6. Show the construction of a 2-to-4-line decoder with an enable input constructed with NAND
gates, construct the corresponding truth table for the same.
Implement the half adder using decoder and multiplexer for the following simplified boolean
function
S x0y xy0
C xy
UNIT IV
7. Explain the process of construction of a master-slave JK flip-flop using NAND gates.
Enumerate the construction of RS flip-flop with the help of logic diagram and characteristic table
for the same.
8. Explain the excitation table for the 3-bit binary counter and write the simplified maps for the
excitation table based on flip-flop input function.
Construct the toggle flip-flop. Derive the characteristic table and characteristic equation.
UNIT V
9. Using PROM, realize the following expressions
F1 P
F2 P
Implement the circuit with a PLA
F1 P
F2 P
10. Implement the Combinational circuit defined by the function with a PAL.
10, 12, 13)
Design a BCD to excess-3 code converter and implement using suitable PLA.
INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
Four Year B.Tech III Semester End Examinations (Supplementary) July, 2018
Regulation: IARE R16
DIGITAL LOGIC DESIGN
Time: 3 Hours (Common to CSE IT) Max Marks: 70
Answer ONE Question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
UNIT I
1. Perform the subtraction operation using complement of the subtrahend
i. (5C)16 (3F)16
ii. (C0)16 (7A)16
Convert the following to the designated bases
a. (1000)2 to gray
b. (22:64)10 to )16
c. (A72F)16 to
2. Write about binary logic in detail and explain binary addition and binary subtraction with
examples.
Explain why Excess- 3 is self complementing code with an example.
UNIT II
3. Write the truth table for DeMorgans theorem by taking an example.
Simplify the boolean function
11; 15) that has the don't-care conditions
4. Implement the following Boolean functions using the following logic
i. using NAND- NAND Realization
ii. using NOR- NOR Realization
Simplify the following using four- variable K-map
i. w0z xz x0y wx0z
ii. B0D A0BC0 AB0C ABC0
Page 1 of 2
UNIT III
5. Explain the working of 2-bit magnitude comparator with the help truth table and logic diagram.
Enumerate the implementation of full-adder using two half-adders and an OR gate, for the
following boolean expressions:
S x0y0z x0yz0 xy0z0 xyz
C xy xz yz
6. Show the construction of a 2-to-4-line decoder with an enable input constructed with NAND
gates, construct the corresponding truth table for the same.
Implement the half adder using decoder and multiplexer for the following simplified boolean
function
S x0y xy0
C xy
UNIT IV
7. Explain the process of construction of a master-slave JK flip-flop using NAND gates.
Enumerate the construction of RS flip-flop with the help of logic diagram and characteristic table
for the same.
8. Explain the excitation table for the 3-bit binary counter and write the simplified maps for the
excitation table based on flip-flop input function.
Construct the toggle flip-flop. Derive the characteristic table and characteristic equation.
UNIT V
9. Using PROM, realize the following expressions
F1 P
F2 P
Implement the circuit with a PLA
F1 P
F2 P
10. Implement the Combinational circuit defined by the function with a PAL.
10, 12, 13)
Design a BCD to excess-3 code converter and implement using suitable PLA.
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