Exam Details
Subject | Modeling And Testing Of Digital Systems | |
Paper | ||
Exam / Course | Diploma In Electronics And Communication Engineering (DECVI)/ Advanced Level Certificate Course In Electronics And Communication Engineering (ACEVI)/ | |
Department | School of Engineering & Technology (SOET) | |
Organization | indira gandhi national open university | |
Position | ||
Exam Date | June, 2016 | |
City, State | new delhi, |
Question Paper
No. of Printed Pages: 3 . IBIELE-ooal
B.Tech. -VIEP -ELECTRONICS AND COMMUNICATION ENGINEERING (BTECVI) Term-End Examination 00296 June, 2016
BIELE-003 MODELLING AND TESTING OF DIGITAL SYSTEMS
Time: 3 hours Maximum Marks: 70
Note: any seven questions. All questions carry equal marks. Missing data, ifany, may be suitably assumed and mentioned. Use of scientific calculator is permitted.
1. With sample waveforms, explain the transport delay and inertial delay in digital circuits. 10
2. Explain structural modelling with an example. Write a VHDL program for detecting the number of in an eight-bit vector, if even number of .output and if odd number of output 10
3. With suitable examples, compare variables and signals in VHDL. 5
Define Generics. Using Generics statement, write a VHDL code for a three input NAND gate. 5
4. Write a VHDL code for the synthesis of a case statement. 5
Explain simulation semantics. 5
5. What is a subprogram? How is it used in VHDL programs Explain with suitable example. 5
What are the real defects in digital circuits Write down the equivalence rules for AND, OR, NAND and NOR gates. 5
6. What are the main reasons of IC malfunction (faults) Explain the various types of faults found in digital circuits with suitable examples. 10
7. Give an algorithm for testing of bridging faults. What are the main consequences of bridging faults in digital circuits? 10
8. Draw and explain Built-In Self-Test (BIST) implementation using Built-In Logic Block Observers (BILBOs). 5
Discuss the various hardware pattern generation approaches of BIST. 5
9. What is boundary scan Draw and explain the test pattern generator block diagram. 10
10. Write short notes on any two of the following: 2x5=10
Packages and Libraries
State machine modelling using VHDL
Testing for single stuck faults
B.Tech. -VIEP -ELECTRONICS AND COMMUNICATION ENGINEERING (BTECVI) Term-End Examination 00296 June, 2016
BIELE-003 MODELLING AND TESTING OF DIGITAL SYSTEMS
Time: 3 hours Maximum Marks: 70
Note: any seven questions. All questions carry equal marks. Missing data, ifany, may be suitably assumed and mentioned. Use of scientific calculator is permitted.
1. With sample waveforms, explain the transport delay and inertial delay in digital circuits. 10
2. Explain structural modelling with an example. Write a VHDL program for detecting the number of in an eight-bit vector, if even number of .output and if odd number of output 10
3. With suitable examples, compare variables and signals in VHDL. 5
Define Generics. Using Generics statement, write a VHDL code for a three input NAND gate. 5
4. Write a VHDL code for the synthesis of a case statement. 5
Explain simulation semantics. 5
5. What is a subprogram? How is it used in VHDL programs Explain with suitable example. 5
What are the real defects in digital circuits Write down the equivalence rules for AND, OR, NAND and NOR gates. 5
6. What are the main reasons of IC malfunction (faults) Explain the various types of faults found in digital circuits with suitable examples. 10
7. Give an algorithm for testing of bridging faults. What are the main consequences of bridging faults in digital circuits? 10
8. Draw and explain Built-In Self-Test (BIST) implementation using Built-In Logic Block Observers (BILBOs). 5
Discuss the various hardware pattern generation approaches of BIST. 5
9. What is boundary scan Draw and explain the test pattern generator block diagram. 10
10. Write short notes on any two of the following: 2x5=10
Packages and Libraries
State machine modelling using VHDL
Testing for single stuck faults
Other Question Papers
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