Exam Details
Subject | digital computer organization | |
Paper | ||
Exam / Course | m.c.a | |
Department | ||
Organization | Alagappa University Distance Education | |
Position | ||
Exam Date | May, 2017 | |
City, State | tamil nadu, karaikudi |
Question Paper
DISTANCE EDUCATION
M.C.A. DEGREE EXAMINATION, MAY 2017.
First Semester
DIGITAL COMPUTER ORGANIZATION
(2010 Academic year onwards)
Time Three hours Maximum 100 marks
SECTION A — × 8 40 marks)
Answer any FIVE questions.
1. Perform the indicated base conversions:
548 to base 5
3124 to base 7.
2. Write the Boolean expression for a four-input NAND
gate.
3. Construct the operation XOR from the basic Boolean
operations AND, OR, and NOT.
4. Design an 1-to-8 demultiplexer.
5. How can you form the negation of an integer in two's
complement representation?
6. Assume numbers are represented in 8-bit two's
complement representation. Show the calculation of the
following: 13 6 13.
7. What is the difference between DRAM and SRAM in
terms of characteristics such as speed, size, and cost?
8. What is the difference between memory-mapped I/O and
isolated
Sub. Code
101
DE-681
2
Ws 11
SECTION B — × 15 60 marks)
Answer any FOUR questions.
9. What is the difference between cannonical form and
stardard form? Which form is preferable when
implementing a Boolean function with gates? Which form
is obtained when reading a function from a truth table?
10. Obtain the simplified expressions in product of sums:
13, 15)
11. Implement full adder circuit with multiplexers.
12. Implement a full subtractor with two half subtractors and
an OR gate.
13. Design a BCD counter with JK flip-flops.
14. Suggest reasons why RAMs traditionally have been
organized as only 1 bit per chip whereas ROMs are
usually organized with multiple bits per chip.
Consider a dynamic RAM that must be given a refresh
cycle 64 times per ms. Each refresh operation requires
150 ns; a memory cycle requires 250 ns. Whet percentage
of the memory's total operating time must be given to
refreshes?
15. When a device interrupt occurs, how does the
processor determine which device issued the
interrupt?
When a DMA module takes control of a bus, and
while it retains control of the bus, what does the
processor do?
M.C.A. DEGREE EXAMINATION, MAY 2017.
First Semester
DIGITAL COMPUTER ORGANIZATION
(2010 Academic year onwards)
Time Three hours Maximum 100 marks
SECTION A — × 8 40 marks)
Answer any FIVE questions.
1. Perform the indicated base conversions:
548 to base 5
3124 to base 7.
2. Write the Boolean expression for a four-input NAND
gate.
3. Construct the operation XOR from the basic Boolean
operations AND, OR, and NOT.
4. Design an 1-to-8 demultiplexer.
5. How can you form the negation of an integer in two's
complement representation?
6. Assume numbers are represented in 8-bit two's
complement representation. Show the calculation of the
following: 13 6 13.
7. What is the difference between DRAM and SRAM in
terms of characteristics such as speed, size, and cost?
8. What is the difference between memory-mapped I/O and
isolated
Sub. Code
101
DE-681
2
Ws 11
SECTION B — × 15 60 marks)
Answer any FOUR questions.
9. What is the difference between cannonical form and
stardard form? Which form is preferable when
implementing a Boolean function with gates? Which form
is obtained when reading a function from a truth table?
10. Obtain the simplified expressions in product of sums:
13, 15)
11. Implement full adder circuit with multiplexers.
12. Implement a full subtractor with two half subtractors and
an OR gate.
13. Design a BCD counter with JK flip-flops.
14. Suggest reasons why RAMs traditionally have been
organized as only 1 bit per chip whereas ROMs are
usually organized with multiple bits per chip.
Consider a dynamic RAM that must be given a refresh
cycle 64 times per ms. Each refresh operation requires
150 ns; a memory cycle requires 250 ns. Whet percentage
of the memory's total operating time must be given to
refreshes?
15. When a device interrupt occurs, how does the
processor determine which device issued the
interrupt?
When a DMA module takes control of a bus, and
while it retains control of the bus, what does the
processor do?
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