Reg. No.
B.E. B.Tech. DEGREE EXAMINATION, MAY 2017
Third Semester
Electronics and Communication Engineering
01UEC302 DIGITAL ELECTRONICS AND DESIGN
(Regulation 2013)
Duration: Three hours Maximum: 100 Marks
Answer ALL Questions
PART A (10 x 2 20 Marks)
1. State Demorgan's theorem.
2. Realize EX-OR Gate from NAND Gate.
3. Write the truth table for full subtractor.
4. Define decoder.
5. Differentiate flip flop and latch.
6. What is the need of state minimization?
7. What is the difference between PAL and PLA?
8. List the different types of memory.
9. List the steps in the design of asynchronous sequential circuits.
10. Compare synchronous and asynchronous sequential circuit.
PART B x 16 80 Marks)
11. Design a logic circuit using minimum number of basic gates for the Boolean expression f
Question Paper Code: 31432
2
31432
Use K map
to reduce the function.
Or
Simplify the following function using tabulation method and implement it using
universal gates. F 13, 14,15).
12. Design and implement an Excess 3 to BCD code converter.
Or
Explain the working of carry look ahead adder.
13. List out the various types of shift registers. With neat diagram explain the Universal
Shift register.
Or
Design a MOD-10 synchronous counter using J-K flip flops. Write the excitation
table and state table.
14. With neat diagram explain the RAM organization.
Or
Implement the following two Boolean functions

using
PLA ii) PAL iii) ROM
15. Design an asynchronous sequential circuit with two inputs X and Y and with one
output Z. Whenever Y is input X is transferred to Z. When Y is the output does
not change for any change in X. Use SR latch for implementation of the circuit.

Or
What is a Hazard? What are the types of hazards? Check whether the following
circuit contains an hazard or not.
Y AB BC
If the hazard is present, how to remove it.