Hall Ticket No:
Question Paper Code B3608
(AUTONOMOUS) M. Tech II Semester End Semester Regular Examinations, June 2017
(Regulations: VCE-R15) HARDWARE SOFTWARE CO-DESIGN
(Embedded Systems) Date: 09 June, 2017 FN
Time: 3 hours
Max Marks: 70
Answer any Five Questions.
All Questions carries equal marks.
1.
Explain the following with respect to generic Co-Design methodology.
7M
Explain the following:
i. Resource cost
ii. Synthesis
iii. Scheduling
7M
2.
Explain the following:
i. Hardware software synthesis algorithms
ii. Hardware software Partitioning
14M
3.
Mention the advantages and disadvantages of Prototyping and emulation.
7M
With a flow diagram, explain the FPGA Configuration process.
7M
4.
With a neat block diagram, explain the architecture of ADSP21070 SHARC.
7M
Explain the following:
i. Mixed systems
ii. Memory Architectures
7M
5.
With a neat block diagram, explain the main phases of a compiler.
7M
With a block diagram, Explain the data flow among Parser, Locator and Loader.
7M
6.
With a neat block diagram, explain the Hardware/software interface.
7M
Explain the following:
i. Pipe line terminology
ii. Semaphores
7M
7.
Explain the following:
i. System level specification Languages
ii. Design representation for system level synthesis
14M
8.
Explain the following:
i. Master Slave Co-Simulation
ii. Distributed Co-Simulation
iii. Distributed C -VHDL Co-Simulation
iv. Inter Simulator Interface Simulation
14M