computer architecture and parallel processing

Vardhaman College Of Engineering

Exam Details

Subject computer architecture and parallel processing
Paper
Exam / Course b.tech
Department
Organization Vardhaman College Of Engineering
Position
Exam Date June, 2017
City, State telangana, hyderabad


Question Paper

Hall Ticket No:
Question Paper Code B3606
(AUTONOMOUS) M. Tech II Semester End Semester Regular Examinations, June 2017
(Regulations: VCE-R15) COMPUTER ARCHITECTURE AND PARALLEL PROCESSING
(Embedded Systems) Date: 05 June, 2017 FN
Time: 3 hours
Max Marks: 70
Answer any FIVE Questions
Each Question carries equal marks
1.
Describe in detail about parallelism in uniprocessor architecture.
7M
Illustrate with a neat diagram, bandwidth balancing mechanisms between CPU, Memory and I/O sub-systems.
7M
2.
Tabulate the characteristics of memory devices in a memory hierarchy.
8M
Illustrate with a neat diagram, how to map an address in a segmented system.
6M
3.
Briefly describe the classification of pipeline processors with suitable diagrams.
6M
List the operations performed in the four pipeline stages.
8M
4.
Write a note on Hazard detection and Resolution.
6M
Discuss the instruction pipeline with both sequential and target prefetch buffers with necessary diagram.
8M
5.
Compare the major architectural features between Star-100 and TI-ASC.
8M
Explain the vector processing in streaming mode.
6M
6.
Explain the instruction format and architecture of the Cray-1.
8M
Describe any six common practices in optimizing the vector functions.
6M
7.
Construct a 1-by-8 de-multiplexer using 2X2 switch boxes.
7M
Illustrate the steps involved in cross-cluster memory access.
7M
8.
Discuss the operating system configurations for a multiprocessor computer.
8M
Write a note on detection of parallelism in programs.
6M


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