Hall Ticket No:
Question Paper Code B3458
(AUTONOMOUS) M.Tech II Semester End Semester Regular Examinations, June 2017
(Regulations: VCE-R15) DESIGN FOR TESTABILITY
(Digital Electronics and Communication Systems) Date: 16 June, 2017 FN
Time: 3 hours
Max Marks: 70
Answer any Five Questions.
All Questions carries equal marks.
1.
Write the binary decision diagram for the following Boolean functions:
i.
ii. f=bcd;
iii. f=ab
7M
Explain the following:
i. Gate level model
ii. Functional block
7M
2.
Explain the different delay models in digital circuits.
7M
Explain:
i. Static and Dynamic Hazards
ii. Transport delay
7M
3.
For the logic circuit in the Fig.1 below, compute:
i. Total number of single stuck-at faults
ii. Total number of single stuck-open faults
iii. Total number of all possible single and multiple stuck-at fault combinations
You can assume that a NOT gates is realized using 2 transistors, 2 input NAND and NOR gates are realized using 4 transistors, and 2 input AND and OR gates are realized using 6transistors each.
Fig.1
7M
For the circuit shown in Fig.2 Generate a test for the fault g s-a-1. Determine all the other faults detected by this test:
Fig.2
7M
4.
Explain:
i. ATPG Vector
ii. Testing for SSF
7M
With a neat block diagram, explain the deterministic test generation system.
7M
5.
With a neat block diagram, explain the operation of Full Isolated Scan.
7M
With a neat block diagram, explain the Scan path arrangement.
7M
Cont…2

6.
With a neat block diagram, explain the type 2(internal-XOR)LFSR.
7M
For an autonomous LFSR, show that if it's initial state is not the all 0 state then it will never enter the all 0 state.
7M
7.
What is BIST? Explain how BIST techniques can be classified.
7M
With a neat block diagram, explain the L0CST architecture.
7M
8.
With a neat block diagram, explain the typical RAM BIST architecture.
7M
Explain the following:
i. JTAG Testing features
ii. Memory Chip Test algorithms
7M