Hall Ticket No:
Question Paper Code B3408
(AUTONOMOUS) M.Tech II Semester Regular/Supplementary Examinations, June 2017
(Regulations: VCE-R15) LOW POWER CMOS VLSI DESIGN
(Digital Electronics and Communication Systems) Date: 09 June, 2017 FN
Time: 3 hours
Max Marks: 70
Answer any Five Questions.
All Questions carries equal marks.
1.
Explain the following:
i. Fundamental limits
ii. Material limits
7M
Derive the expression for dynamic power dissipation of CMOS inverter.
7M
2.
Given Y=X1X2+ X2X3 where 3 are mutually independent. If Z=X1X2+y. Determine and
7M
Draw the binary decision diagram and write multiplier implementation for the function y=AB+BC+AC.
7M
3.
Explain the following:
i. Power sensitivity and its estimation
ii. Static Hazard
III. Dynamic Hazard
iv. Monte Carlo based technique for combinational circuits
14M
4.
With a neat block diagram, explain the pre-computation architecture.
7M
With a neat block diagram, explain the parallel implementation.
7M
5.
Explain the following with respect to synthesis for low power:
i. State assignment for finite state machines
ii. Technology mapping
iii. Transistor sizing
iv. Power optimization using operation substitution
14M
6.
With a neat circuit diagram, explain the operation of 6T SRAM cell.
7M
Explain the following with respect to SRAM:
i. Sense amplifiers
ii. Pre-charge differential read/write schemes
7M
7.
With a neat circuit diagram, explain the operation of differential charge amplifier.
7M
With a neat block diagram, explain the divided word line architecture.
7M
8.
Explain the following:
i. Software design for power estimation
ii. Reversible logic
iii. Voltage island
14M