Exam Details
Subject | computer organization and architecture | |
Paper | ||
Exam / Course | b.tech | |
Department | ||
Organization | Institute Of Aeronautical Engineering | |
Position | ||
Exam Date | November, 2018 | |
City, State | telangana, hyderabad |
Question Paper
Hall Ticket No Question Paper Code: ACS004
INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
Four Year B.Tech III Semester End Examinations (Regular) November, 2018
Regulation: IARE R16
COMPUTER ORGANIZATION AND ARCHITECTURE
Time: 3 Hours (Common to CSE IT) Max Marks: 70
Answer ONE Question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
UNIT I
1. Briefly explain CPU internal organization with neat sketch.
Show the internal linear organization of an 8X2 ROM chip and explain it.
2. Show the code to perform the computation X using microprocessors that use
the following instruction formats. Do not modify the values of and D. If necessary use
temporary location T to store intermediate results.
i. Three- operand instructions
ii. Two-operand instructions
iii. One- operand instructions
iv. Zero-operand instructions
Discuss about the addressing modes in assembly language in detail.
UNIT II
3. Explain in detail about RTL and specify a memory for the memory operation in each case.
i. R2
ii. R3
iii. R5
Describe Register transfer and list out the basic symbols for Register transfers.
4. Define the micro instruction format with suitable example.
Demonstrate the micro programmed control organization.
UNIT III
5. Describe the instruction formats with neat sketch and Explain different fields of an instruction
format.
Describe an instruction cycle and its various phases with a flow chart.
Page 1 of 2
6. Draw flowchart and explain addition and subtraction of floating point numbers in detail.
Illustrate BCD adder which contains two four bit binary adders with the block diagram.
UNIT IV
7. Explain Direct Memory Access Controller functionality with the block diagram.
A block of data is to be transferred between I/O device and processor, explain how this can be
accomplished using DMA operation?
8. Show how virtual address mapped with memory hierarchy with a neat sketch.
Explain modes of transfer for transferring information from CPU to other devices.
UNIT V
9. How speed up happens when instructions executed through pipelining? Prove it.
Explain pipeline processing in instruction stream with an example.
10. Explain in detail about cross bar switching inter connection of multi processor system.
Discuss semaphore in interprocess communication in proper functionality of multiprocessor system.
INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
Four Year B.Tech III Semester End Examinations (Regular) November, 2018
Regulation: IARE R16
COMPUTER ORGANIZATION AND ARCHITECTURE
Time: 3 Hours (Common to CSE IT) Max Marks: 70
Answer ONE Question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
UNIT I
1. Briefly explain CPU internal organization with neat sketch.
Show the internal linear organization of an 8X2 ROM chip and explain it.
2. Show the code to perform the computation X using microprocessors that use
the following instruction formats. Do not modify the values of and D. If necessary use
temporary location T to store intermediate results.
i. Three- operand instructions
ii. Two-operand instructions
iii. One- operand instructions
iv. Zero-operand instructions
Discuss about the addressing modes in assembly language in detail.
UNIT II
3. Explain in detail about RTL and specify a memory for the memory operation in each case.
i. R2
ii. R3
iii. R5
Describe Register transfer and list out the basic symbols for Register transfers.
4. Define the micro instruction format with suitable example.
Demonstrate the micro programmed control organization.
UNIT III
5. Describe the instruction formats with neat sketch and Explain different fields of an instruction
format.
Describe an instruction cycle and its various phases with a flow chart.
Page 1 of 2
6. Draw flowchart and explain addition and subtraction of floating point numbers in detail.
Illustrate BCD adder which contains two four bit binary adders with the block diagram.
UNIT IV
7. Explain Direct Memory Access Controller functionality with the block diagram.
A block of data is to be transferred between I/O device and processor, explain how this can be
accomplished using DMA operation?
8. Show how virtual address mapped with memory hierarchy with a neat sketch.
Explain modes of transfer for transferring information from CPU to other devices.
UNIT V
9. How speed up happens when instructions executed through pipelining? Prove it.
Explain pipeline processing in instruction stream with an example.
10. Explain in detail about cross bar switching inter connection of multi processor system.
Discuss semaphore in interprocess communication in proper functionality of multiprocessor system.
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