Hall Ticket No Question Paper Code: BES005
INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
M.Tech II Semester End Examinations (Regular Supplementary) July, 2018
Regulation: IARE-R16
FPGA ARCHITECURE AND APPLICATIONS

Time: 3 Hours Max Marks: 70
Answer ONE Question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
UNIT I
1. Implement the following boolean expressions using PAL
A0 AB BC
AC AB
Also write PAL programmable table.
Draw and explain the general block diagram of CPLD.
2. Distinguish between ROM, PLA and PAL.
What are advantages of CPLD over PLA and PAL?
UNIT II
3. With examples, explain about look up tables in FPGA.
Distinguish between Anti-fuse technology and SRAM technology.
4. Implement the realization of Half Adder circuit using FPGA.
Explain the need of programmable interconnects in FPGA.
UNIT III
5. With a block diagram, explain about Xilinx 4000 series input/output block.
Explain about general purpose interconnect in Xilinx 3000 Series.
6. With block diagram, explain about CLB block in Xilinx 3000 series.
With block diagram, explain about XC2000 series input/output block.
UNIT IV
7. Explain how Actel ACT-1 logic module acts as a boolean function generator.
Explain about Actel ACT-1 programmable interconnect architecture.
8. Explain about sequential logic module of Actel ACT-2.
Explain about the speed performance of Actel ACT-1, 3.
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UNIT V
9. Explain the procedure of designing adders with ACT devices.
Write short notes on design issues in implementing a digital design.
10. Describe the operation of fast video controller for a robot manipulator.
Write short notes on fast DMA controller mechanism with relavant block diagrams.