VARDHAMAN COLLEGE OF ENGINEERING
(AUTONOMOUS)
B. Tech VI Semester Regular Examinations, May 2018
(Regulations: VCE-R15)
CMOS VLSI DESIGN
(Electronics and Communication Engineering)
Date: 17 May, 2018 FN Time: 3 hours Max Marks: 75
Answer ONE question from each Unit
All Questions Carry Equal Marks
Unit I
1. What is threshold voltage in MOSFETs? Explain with equation. 5M
With relevant equations, explain the DC characteristics of CMOS inverter?
10M
2. Explain Wafer processing and Oxidation in CMOS technology. 8M
Briefly explain the physical origin of Latch up in CMOS circuits.
7M
Unit II
3. Define and explain symmetrical inverter with voltage transfer characteristics. 7M
Illustrate with relevant equations the power dissipation in CMOS inverter.
8M
4. Explain the following:
i. Noise Margin
ii. Sizing of a transistor
6M
Draw the layout of symmetric inverter and with
2 140 n
A
k
V

VTn 0.7V
2 60 p
A
k
V


0.7 Tp V V 3 DD V V . Calculate M V
i. When n p
ii. When
n p
W W
L L



9M
Unit III
5. Explain the CMOS SRAM cell with the help of neat diagram. 10M
Draw the CMOS schematic and layout of the f
5M
6. Derive the gate mid-point voltage equation M V for NOR2 CMOS gate. 7M
Describe the operation of CMOS Schmitt trigger circuit with neat waveform response
and voltage transfer characteristics.
8M
Unit IV
7. Explain the Transmission gate full adder along with relevant circuits. 7M
Implement 2:1 multiplexer 4:1 multiplexer using transmission gate
8M
8. Illustrate Logic-0 transfer in transmission gate using electrical analysis. 7M
Describe the operation of Transmission Gate based Flip-Flop.
8M
Unit V
9. Explain the concept of junction reverse leakage current in MOSFETs. 7M
Discuss the factors on which sub threshold leakage current depends upon along with
relevant equations.
8M
10. Explain in detail the Dynamic RAM cell. 10M
Explain with an example the clocked CMOS circuit.
5M