M.Sc. (Semester IV) (CGPA) Examination Oct/Nov-2017
Material Science
MICROELECTRONICS
Day Date: Friday, 17-11-2017 Max. Marks: 70
Time: 02.30 PM to 05.00 PM
Instructions: and are compulsory.
Answer any three questions from Q.3 to Q.7.
Use of non-programmable calculator is allowed
All questions carry equal marks.
Q.1 Objective questions: 06
In the purification of silicon process, the segregation co-efficient
is defined by
None of the mentioned
The electron-beam instruments used extensively for VLSI are
Scanning Electron Microscope
Transmission Electron Microscope
Auger Electron Spectrometer
All of the mentioned
State True or False: 08
In the Silicon crystal structure, the defects influence the optical,
electrical and mechanical properties.
2 SiO used as metallic film in the thin film resistor.
Molecular Beam Epitaxy is a type of CVD epitaxial process that uses
evaporation method.
Optical lithography includes the formation of images with visible or UV
radiation in a photoresist.
Reactive Ion Etching is also called as reactive sputter etching.
Boron is a n-type material, whereas Phosphorous is an p-type
material.
The maximum lead available in a metal can IC package is 12.
GaAs is more difficult to grow in crystal form and Ge crystal will be
destroyed at high temperature.
Q.2 Write short notes:
Dielectric Characteristics of the Substrates 05
Evaluation of grown layer 04
Flat package 05
Q.3 Discuss wet chemical etching technique. 06
Distinguish between VPE, LPE and MBE techniques. 08
Q.4 Explain the optical lithography technique. 06
With necessary theory and schematic, describe in detail the Czochralski
crystal growth technique of crystal growth.
08
Q.5 Discuss Molecular beam epitaxy technique with a neat sketch. 06
Discuss Chemical vapour deposition technique for the deposition of
silicon nitride films.
08
Q.6 Write a note on ohmic contact. 06
With a neat schematic, explain the magnetron sputtering technique. 08
Q.7 Write a note on encapsulation and package sealing. 06
With relevant diagrams, explain the masking sequence and process flow
of n-MOS devices.