SYMCA (Part (Under Faculty of Engg.) Examination, 2017
COMPUTER ORGANIZATION AND ARCHITECTURE
Day and Date Tuesday, 9-5-2017 Total Marks 100
Time 3.00 p.m. to 6.00 p.m.
1. MCQ 20
Pipe-lining is a unique feature of
RISC CISC
ISA IANA
The computer architecture aimed at reducing the time of execution of
instructions is
CISC RISC
ISA ANNA
The read and write operations usually start at of the sector.
Centre Middle
From the last used point Boundaries
The access time is composed of
Seek time Rotational delay
Latency Both a and b
The disadvantage/s of the hardwired approach is
It is less flexible
It cannot be used for complex instructions
It is costly
Both a and b
For the synchronization of the read head, we make use of a
Framing bit Synchronization bit
Clock Dirty bit
Seat
No.
SLR-L 13
The main aim of virtual memory organisation is
To provide effective memory access
To provide better memory transfer
To improve the execution of the program
All of the above
The number successful accesses to memory stated as a fraction is called as

Hit rate Miss rate
Success rate Access rate
The algorithm to remove and place new contents into the cache is called

Replacement algorithm Renewal algorithm
Updation None of the above
10) The effectiveness of the cache memory is based on the property of
Locality of reference Memory localisation
Memory size None of the above
11) The memory which is used to store the copy of data or instructions stored in
larger memories, inside the CPU is called
Level 1 cache Level 2 cache
Registers TLB
12) The DMA transfer is initiated by
Processor The process being executed
I/O devices OS
13) The DMA controller has registers.
4 2
3 1
14) Interrupts initiated by an instruction is called as
Internal External
Hardware Software
15) Which interrupt is unmask able
RST 5.5 RST 7.5
TRAP Both a and b
16) The return address from the interrupt service routine is stored on the
System heap Processor register
Processor stack Memory
17) The method which offers higher speeds of I/O transfers is
Interrupts Memory mapping
Program-controlled I/O DMA
18) The most efficient way of handling parameter passing is by using
General purpose registers Stacks
Memory locations None of the above
19) Physical memory is divided into sets of finite size called as
Frames Pages
Blocks Vectors
20) The addressing mode, where you directly specify the operand value is
Immediate Direct
Definite Relative
SECTION I
2. Write short note on any 4
RISC and CISC characteristics.
Memory-reference instructions.
Register Stack.
Major components of CPU.
Subroutines.
3. Answer the following
Explain instruction formats and addressing modes. 10
What is micro program Explain micro programmed control organization in
detail. 10
OR
Explain interrupts and its cycle in detail. 10
SECTION II
4. Write short note on any 4
Instruction pipeline.
Virtual memory.
Direct-Memory Access
Handshaking.
Input-Output interface.
5. Answer the following
Explain Addressing Modes in detail. 10
What is interrupt Explain different types of interrupts. 10
OR
Explain Register stack and Memory stack in detail. 10