M.Sc. DEGREE EXAMINATION, NOVEMBER 2017
Third Semester
Electronics
DIGITAL SIGNAL PROCESSOR PROGRAMMING AND
APPLICATIONS
(CBCS 2015 onwards)
Time 3 Hours Maximum 75 Marks
Part A (10 x 2 20)
Answer all the questions.
1. How do you represent the number x 4 using fixed
point representation?
2. Define compensation filter.
3. Write the role of program counter.
4. Define pipeline.
5. List the on-chip peripherals of TMS320C54xx.
6. Define assembler.
7. Define wait states.
8. What is CODEC?
9. Define system-on-a-chip.
10. What is circular buffering in DSP?
Sub. Code
5MEL3C3
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Wk 14
Part B x 5 25)
Answer all the questions.
11. Explain double-precision fixed-point format and
block floating-point format for signals and
coefficients in DSP systems.
Or
Describe the sources of error in DSP
implementations for evaluating the computational
accuracy.
12. Explain the basic program sequence of
programmable DSP devices.
Or
Draw the block diagram of Harvard architecture
and explain.
13. Write short note on internal memory and memory
mapped register of TMS320C54xx.
Or
Illustrate the interrupts programming models with
suitable examples.
14. With the aid of suitable timing diagrams explain
the memory interface signals for a read-write
sequence of operations to programmable DSP
devices.
Or
Describe the interfacing concept of parallel I/O to
programmable DSP devices with neat sketch.
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15. Differentiate the digital signal processors and
microcontrollers.
Or
Write short note on DSP based biotelemetry
receiver.
Part C x 10 30)
Answer any three questions.
16. Describe the DSP computational errors for evaluating
computational accuracy in DSP implementations.
17. Draw and explain the block diagram of a digital signal
processing system.
18. Explain various addressing modes of a digital signal
processor TMS320C54xx.
19. With neat diagram, explain the operation of Direct
Memory Access (DMA).
20. With neat sketch, explain how the hard disk drive is
going to be interfaced to programmable DSP devices.
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